Efficient Hardware Reduction of FIR Filter for Parallel Data in Mixed Signal Processing

The paper presents a novel method of structure for designing and implementation of hardware reduced FIR filter in mixed signal processing domain for parallel data processing. Supported by a review of the literature, the paper demonstrates that the proposed methodology is superior, economical and can be applied in to applications like biomedical and audio signals. The results show improved performance and cost reduction, which has practical implications in terms of applications. General Terms Subband, passband, lowpass filter, mixed signal domain, ADC, DAC, FIR, Hardware reduction, parallel data in mixed signal processing, efficient hardware reduction.